One critical factor that determines the feasibility of employing carbon nanotubes as channel materials for post-silicon logic devices is the process compatibility to the current CMOS process flow. We show a wafer-scale integration scheme of carbon nanotube field-effect transistor (CNFET) that is performed by 8″ production tools. High density CNT arrays were transferred on the processed wafer, and high performance CNFET with an excellent subthreshold slope (88 mV /decade) is demonstrated. We further show that the work-function tuning enabled by the conventional gate doping can be achieved in our novel embedded poly-Si gate structure. Approximate Vt change of 0.6V, from n-gate to p-gate, is observed. The Vt shift being smaller than the gate work function difference can be attributed to the Fermi level pinning between poly-Si and high-k interface.
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机译：确定使用碳纳米管作为用于后硅逻辑器件的通道材料的一个关键因素是对电流CMOS工艺流程的过程兼容性。我们展示了由8“生产工具执行的碳纳米管场效应晶体管（CNFET）的晶片级集成方案。高密度CNT阵列在加工后的晶片上转移，并且对具有优异亚阈值斜率（88mV /十年）的高性能CNFET进行了说明。我们进一步表明，在我们的新型嵌入式多Si栅极结构中可以实现由传统栅极掺杂所启用的工作功能调整。观察到从N栅极到P门的0.6V的近似V T 更改。 V T 换档小于栅极工作函数差异可以归因于POVER-SI和HIGH-K接口之间的费米级别钉。
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