RET Masks for the Final Frontier of Optical Lithography

摘要

With immersion and hyper numerical aperture (NA>1) optics apply to the ITRS 2003/4 roadmap scenario (Figure 1); it is very clear that the IC manufacturing has already stepped into the final frontier of optical lithography. Todayis advanced lithography for DRAM/Flash is operating at k_1 close to 0.3. The manufacturing for leading edge logic devices does not follow too far behind. Patterning at near theoretical lithography imaging limit (k_1=0.25) even with hyper NA optics, the attainable aerial image contrast is marginal at best for the critical feature. Thus, one of the key objectives for low k_1 lithography is to ensure the printing performance of critical features for manufacturing. Resolution enhancement technology (RET) mask in combination with hyper NA and illumination optimization is one primary candidate to enable lithography manufacturing at very low k_1 factor. The use of rule-based Scattering Bars (SB) for all types of phase-shifting masks has become the de facto OPC standard since 180nm node. Model-based SB OPC method derives from interference mapping lithography (IML) has shown impressive printing result for both clear (gate) and dark field (contact and via) mask types. There are four basic types of RET mask candidates for 65nm node, namely, alternating phase-shifting mask (altPSM), attenuated PSM (attPSM), chromeless phase lithography (CPL) PSM, and double dipole lithography (DDL) using binary chrome mask. The wafer printing performances from CPL and DDL have proven both are strong candidates for 45nm nodes. One concern for using RET masks to target 45 nm nodes is likely to be the scaling for SB dimension for 4X mask. To assist imaging effectively with high NA, SB cannot be too small in width. However, for SB to be larger than sub-resolution, they can easily cause unwanted SB printing. The other major concern is the unwanted side lobe printing. This may occur for semi-dense pitch ranges under high NA and strong off-axis-illumination (OA1). Looking ahead, for manufacturing at 45 nm and 32nm nodes, one challenge is to break through the so-called k_1 barrier (0.25). Multiple exposure schemes in conjunction with RET masks is our proposed solution.