SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test Variation Tolerant Design

机译：工艺变化下规模技术中的SRAM：失效机理，测试和变化容忍设计

获取原文

页面导航

摘要
著录项
相似文献
相关主题

摘要

The inter-die and intra-die variations in process parameters (in particular, threshold voltage (Vt)) can lead to large number of failures in an SRAM array, thereby, degrading the design yield in nanometer technologies. To improve parametric yield of nano-

机译：芯片间和芯片内工艺参数（特别是阈值电压（Vt））的变化会导致SRAM阵列出现大量故障，从而降低纳米技术的设计良率。为了提高纳米级的参量

著录项

来源
《Custom Integrated Circuits Conference, 2006 IEEE》|2006年|P.547-554|共8页
会议地点
作者
Mukhopadhyay; S.; Agarwal; A.; Qikai Chen; Roy; K.;
展开▼
作者单位

展开▼
会议组织
原文格式 PDF
正文语种
中图分类工业技术;
关键词
SRAM chips; circuit testing; process design; SRAM; adaptive body biasing; built-in-self-test; error correcting codes; failure mechanisms; nano-scaled memories; nanometer technologies; parametric yield; process variations; scaled technologies;

机译：SRAM芯片;电路测试;工艺设计; SRAM;自适应偏置;内置自我测试;纠错码;故障机制;纳米级存储器;纳米技术;参数合格率;工艺变化;规模化技术;

相似文献

外文文献
中文文献
专利

1. Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology [J] . Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, Journal of Low Power Electronics . 2011,第2期

机译：基于工艺变化容忍Finfin的32 nm技术的低功耗SRAM单元设计
2. Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations [J] . Qikai Chen, Mahmoodi H., Bhunia S., IEEE transactions on very large scale integration (VLSI) systems . 2005,第11期

机译：通过优化的行进顺序和新颖的DFT技术对SRAM进行高效测试，以应对由于工艺变化而引起的新出现的故障
3. Probability calculation of read failures in nano-scaled SRAM cells under process variations [J] . Hossein Aghababa, Behzad Ebrahimi, Ali Afzali-Kusha, Microelectronics & Reliability . 2012,第11期

机译：过程变化下纳米级SRAM单元中读取失败的概率计算
4. SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test Variation Tolerant Design [C] . Mukhopadhyay, S., Agarwal, Custom Integrated Circuits Conference, 2006 IEEE . 2006

机译：工艺变化下规模技术中的SRAM：失效机理，测试和变化容忍设计
5. Ultralow power and process variation tolerant VLSI circuit design in nano-scale technologies [D] . Hwang, Myeong-Eun. 2007

机译：纳米技术中的超低功耗和耐工艺变化VLSI电路设计
6. Power optimized variation aware dual-threshold SRAM cell design technique [O] . Aminul Islam, Mohd Hasan 2011

机译：功耗优化的变化感知双阈值SRAM单元设计技术
7. A Discussion on RTN Variation Tolerant Guard Band Design Based on Approximation Models of Long-Tail Distributions for Nano-Scaled SRAM Screening [O] . Worawit Somha, Hiroyuki Yamauchi 2013

机译：基于长尾分布近似模型的RTN容错保护带设计的讨论，用于纳米尺度SRAM筛选

SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test Variation Tolerant Design

摘要

著录项

相似文献

相关主题

期刊订阅