首页> 外文会议>Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International >Atomic-layer-deposited ultrathin Si-nitride gate dielectrics - a better choice for sub-tunneling gate dielectrics
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Atomic-layer-deposited ultrathin Si-nitride gate dielectrics - a better choice for sub-tunneling gate dielectrics

机译:原子层沉积的超薄氮化硅栅电介质-亚隧道栅电介质的更好选择

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The suitability of atomic-layer-deposited (ALD) Si nitride to meet the crying need for gate dielectrics with an EOT in the territory of 1 nm, has been investigated through an extensive and comparative study with conventional SiO/sub 2/ gate dielectrics. ALD Si nitride showed excellent reliability characteristics in all standard evaluations of MOS capacitors. Though the inversion layer mobility was slightly smaller for n-MOSFETs with an ALD Si nitride than for a SiO/sub 2/ gate dielectric, post-stress mobility degradation was much less for the ALD samples than for SiO/sub 2/ samples. The lower interface and bulk trap generation rates consistently explain the soft breakdown (SBD) free phenomena and the reduced mobility degradation for the ALD Si-nitride dielectrics. Therefore, the ALD Si-nitride dielectrics would be a better choice for sub-tunneling gate dielectrics.
机译:通过对常规SiO / sub 2 /栅极电介质进行广泛的比较研究,研究了原子层沉积(ALD)氮化硅满足EOT在1 nm范围内的栅极电介质的迫切需求的可行性。 ALD氮化硅在MOS电容器的所有标准评估中均表现出出色的可靠性。尽管具有ALD Si氮化物的n-MOSFET的反型层迁移率略小于SiO / sub 2 /栅极电介质,但ALD样品的应力后迁移率降低要比SiO / sub 2 /样品小得多。较低的界面和体陷阱的生成速率一致地解释了无软击穿(SBD)现象和ALD氮化硅电介质迁移率降低的降低。因此,对于子隧道栅电介质,ALD氮化硅电介质将是更好的选择。

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