Analysis and compact modeling of lateral DMOS power devices under ESD stress conditions

摘要

The detailed physical mechanisms specific for 40V-LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated by means of TLP measurements / HBM testing, EMMI measurements, and 2D-Device simulations. Inhomogeneous triggering caused by device topology as well as the sustained non-homogenous current flow due to the unusual electrical behavior are analyzed in single-and multifinger devices. An existing ESD-MOS compact model is extended according to the investigated phenomena. It successfully describes the LDMOS high current behavior.