A detailed study of the copper contaminating step was performed during the integration of Cu metallization in a dual damascene architecture for sub-quarter micron CMOS technology. Dielectric deposition on copper was shown to be critical for SiO/sub 2/ contamination. Both the SiO/sub 2/ insulator and the etch-stop layer surface can be efficiently cleaned by using dilute HF before subsequent processing. However, this solution was shown not to be effective with inorganic antireflective coatings used for line level photolithography, which are contaminated during chemical mechanical polishing, so a complete removal of this film should be performed during integration.
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机译:针对亚四分之一微米CMOS技术的双镶嵌结构中的铜金属化集成过程中,对铜污染步骤进行了详细研究。铜上的介电沉积对于SiO / sub 2 /污染至关重要。 SiO / sub 2 /绝缘体和蚀刻终止层表面均可在后续处理之前通过使用稀HF进行有效清洁。但是,该溶液对用于线级光刻的无机抗反射涂层无效,该涂层在化学机械抛光过程中被污染,因此在集成过程中应完全去除该膜。
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