Overview of Cu contamination during integration in a dual damascene architecture for sub-quarter micron technology

摘要

A detailed study of copper contaminating steps performed during integration of multilevel Cu metallisation in dual damascene architecture has been performed. Contamination at the wafer back and the bevel edge should make it difficult to use the same equipment for conventional technology and new copper based technology. Several barrier materials have been claimed as efficient against copper diffusion. However, during process integration, contamination issues will be faced before deposition of the barrier layers. Heavy contamination can occur either during Cu chemical mechanical polishing (CMP) or during dielectric etching and via opening on top of contacted copper lines. These residues, concentrated at the dielectric surface, could result in current leakage and shorts between interconnection lines. Several cleaning solutions to remove metal contamination are reviewed and their efficiencies are compared.