Unlocking the Full Potential of Heterogeneous Accelerators by Using a Hybrid Multi-Target Binary Translator

摘要

Embedded systems comprise multiple accelerators to exploit both Instruction and Data-Level parallelism, maximizing performance per watt. However, the use of accelerators usually involves changes in the source code, not maintaining binary compatibility and increasing time-to-market. Therefore, Binary Translation (BT) mechanisms emerge as an alternative, since they dynamically detect and transform parts of the application for optimization without needing any prior modification in the code. Nevertheless, the available BT approaches are limited to one single accelerator, which may not always result in the optimal energy-performance trade-off, since parts of an application may have code that will benefit the most from one accelerator or another depending on its available intrinsic parallelism. Given that, this work proposes a Hybrid Multi-target Binary Translator (HMTBT). Our HMTBT is capable of transparently translating code to different accelerators: a CGRA (Coarse-Grained Reconfigurable Architecture) and a NEON engine, and automatically dispatching the translation to the most well-suited one, according to the type of the available parallelism (ILP or DLP) at the moment. HMTBT improves performance by 54% and 76% and saves energy by 15% and 25% when comparing to a BT targeting a CGRA only and another targeting a NEON engine only. We also compare the HMTBT to a system that features both CGRA and NEON BT mechanisms, showing 12% of energy savings and 14% of performance improvements, on average.