System-on-Chip integration of heterogeneous accelerators for perceptual computing.

摘要

Traditional microprocessor design has seen radical shifts over the past few years. The challenges of excessive power consumption led to the shift from faster and more complex processors to multiple cores on the same chip. More recently, there has been a growing trend towards integrating multiple customized cores instead of homogeneous arrays of processors. The distinction between embedded heterogeneous System-on-Chip (SoC) Architectures and mainstream processor architectures is blurring. A key challenge in both these domains is to efficiently integrate these accelerators in a single chip.;This dissertation contributes towards making the design of system-on-a-chip architectures more flexible, more programmable, and easier to develop and verify. Specifically, a communication and interface framework to integrate heterogeneous accelerators for this domain is proposed. This framework has been incorporated to develop SoC designs for two different perceptual computing applications, visual perception and wireless body-area networks (WBANs). Perceptual computing applications perceive intent by sensing and monitoring different activities of a person and their environments. To support visual perception, a system for detecting, tracking and recognizing objects has been built using the proposed framework. A system has also been developed for supporting compressed sensing of medical signals from the human body for perceptual medical diagnostic applications. These two frameworks demonstrate the flexibility of the framework to compose different systems.;This dissertation also contributes to the design of approximate computing techniques for design of energy-efficient systems. These techniques leverage the programmable aspect of the proposed communication/interface framework. First, the complexity of computation is varied based on relative salience of an object in a visual scene to expend non-uniform effort on an entire scene while providing a quality of output similar to expending same effort across the scene. Second, mathematical approximations are employed to reduce the effort of computation for reconstruction of compressed signals without significant loss of accuracy.;The proposed framework has also been validated through adoption by other researchers in their SoC integration efforts. This research opens new directions in dynamic configuration of accelerators that will form part of future research.