声明
摘要
ABSTRACT
Contents
List of Figures
List of Tables
Chapter 1 Introduction
1.1 Background and Related Work
1.2 Problem Statement
1.3 Thesis Outline
Chapter 2 Optimization of Core Processor Architecture
2.1 Instruction Decompressor Design
2.1.1 FlexCore Processor Architecture
2.1.2 Flexible Datapath Interconnect
2.1.3 The FlexSoC Framework
2.1.4 Existing Compression Schemes
2.1.5 Implementation of Compression scheme
2.1.6 Instruction Decompressor
2.1.7 Implementation of Instruction Decompressor
2.1.8 Discussion on Synthesis Results
2.2 Arithmetic Logic Unit Design
2.2.1 ALU Design-Verification
2.2.2 ALU Design-Basic Synthesis
2.2.3 ALU Design-Design Respin and Power analysis
2.2.4 ALU Design-Place and Route
2.3 Conclusion
Chapter 3 Application Specific Accelerator Design
3.1 CORDIC Accelerator Design
3.1.1 Standard CORDIC Algorithm
3.1.2 Hardware Mapping of Standard CORDIC
3.1.3 Standard CORDIC Hardware Accelerator
3.1.4 Modified CORDIC Algorithm
3.1.5 Modified CORDIC Hardware Accelerator
3.2 CRC Accelerator Design
3.2.1 CRC Computation Techniques
3.2.2 CRC Accelerator Implementation
3.2.3 Integration of CRC Accelerator with MicroBlaze
3.3 Viterbi Accelerator Design
3.3.1 Convolutional Encoding and Viterbi Decoding
3.3.2 Initial Viterbi Decoder
3.3.3 Mixed HW/SW Viterbi Accelerator
3.3.4 Integration of Viterbi Accelerator with MicroBlaze
3.4 Conclusion
Chapter 4 Heterogeneous Architectures
4.1 Digital Hearing Aid
4.1.1 Types of Hearing Aids
4.1.2 Signal Processing Techniques
4.1.3 Basic Description of System
4.1.4 Mixed Hardware/Software Implementation
4.1.5 Hardware Implementation
4.2 Distance and Speed Measurement
4.2.1 Software Implementation
4.2.2 Mixed Hardware/Software Implementation
4.2.3 Hardware Implementation
4.2.4 ASIC Implementation
4.3 Conclusion
Chapter 5 Conclusion and Future Directions
5.1 Summary
5.2 Future Directions
References
Acknowledgments
List of Publications