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Gate Insulator Influences on the Electrical Performance of Back-Channel-Etch Amorphous Zinc Tin Oxide (a-ZTO) Thin Film Transistors

机译:栅极绝缘体对反向沟道刻蚀非晶氧化锌锡(a-ZTO)薄膜晶体管的电性能的影响

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Back-channel-etch amorphous zinc tin oxide thin film transistors (a-ZTO TFTs) are fabricated with various thicknesses and deposition rates of gate insulator (GI). The devices exhibit a higher field-effect mobility and better electrical stress stability with GI thickness decreasing. Furthermore, field-effect mobility and electrical stress stability can be improved by slow GI deposition rate, caused by smoother GI surface. Moreover, combining with percolation theory, we propose a ZTO carrier transport model to explain the experimental phenomenon. The optimized device exhibits good electrical performances: modest saturation mobility of 10 cm2/Vs, on/off ratio > 108 and subthreshold swing of 0.60V/dec. Besides, Vth shift under negative and positive Vgs is −0.28V and +0.17V, respectively.
机译:制造具有各种厚度和栅极绝缘体(GI)沉积速率的背沟道蚀刻非晶氧化锌锡薄膜晶体管(a-ZTO TFT)。随着GI厚度的减小,这些器件表现出更高的场效应迁移率和更好的电应力稳定性。此外,由于较光滑的GI表面而导致的GI沉积速度较慢,因此可以改善场效应迁移率和电应力稳定性。此外,结合渗流理论,我们提出了ZTO载流子传输模型来解释实验现象。经过优化的器件具有良好的电气性能:10 cm的适度饱和迁移率 2 / Vs,开/关比> 10 8 亚阈值摆幅为0.60V / dec。此外,V 在负V和正V下移动 gs 分别为−0.28V和+ 0.17V。

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