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Gate Insulator Influences on the Electrical Performance of Back-Channel-Etch Amorphous Zinc Tin Oxide (a-ZTO) Thin Film Transistors

机译:栅极绝缘体对后沟道蚀刻非晶锌氧化锌(A-ZTO)薄膜晶体管的电气性能影响

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Back-channel-etch amorphous zinc tin oxide thin film transistors (a-ZTO TFTs) are fabricated with various thicknesses and deposition rates of gate insulator (GI). The devices exhibit a higher field-effect mobility and better electrical stress stability with GI thickness decreasing. Furthermore, field-effect mobility and electrical stress stability can be improved by slow GI deposition rate, caused by smoother GI surface. Moreover, combining with percolation theory, we propose a ZTO carrier transport model to explain the experimental phenomenon. The optimized device exhibits good electrical performances: modest saturation mobility of 10 cm2/Vs, on/off ratio > 108 and subthreshold swing of 0.60V/dec. Besides, Vth shift under negative and positive Vgs is ?0.28V and +0.17V, respectively.
机译:背部通道 - 蚀刻非晶锌氧化锡(A-ZTO TFT)由栅极绝缘体(GI)的各种厚度和沉积速率制造。该装置具有更高的场效应迁移率和具有Gi厚度的更好的电应力稳定性。此外,通过慢的GI沉积速率,可以提高现场效应迁移率和电应力稳定性,由更慢的GI表面引起。此外,与渗透理论相结合,我们提出了一种ZTO载波运输模型来解释实验现象。优化的装置表现出良好的电气性能:适度的饱和流动性为10厘米 2 / vs,开/关比> 10 8 和划分0.60V / Dec的划线摇摆。此外,V. th 在负面和正面v下的转变 gs 是?0.28V和+ 0.17V。

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