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Substrate Condition and Metrology Considerations in Poly Gate Doping Implants

机译:多晶硅栅掺杂注入中的衬底条件和计量学考虑

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The evolution from planar to 3D structures in advanced memory devices has resulted in semiconductor equipment manufacturers facing unprecedented challenges in delivering products that can demonstrate simultaneous compliance to the productivity, reliability and process requirements of their customers. In the field of ion implantation, these challenges are driven by: (i) the increasing prevalence of hard mask and removal of PR stripping process and (ii) the transition from the use of implants in dopant application to that of materials modification. These have resulted in large reductions in both the particle size and number density that can be tolerated from implant steps.One area where these issues have proven challenging is that of contact engineering. Low energy phosphorus implants are used to improve the contact resistivity of poly Si contact. This is critical for the read/write time of the storage node capacitor in DRAM operation. As devices shrink further, the thickness of the poly gate in the peripheral transistors become as low as a few hundred Å. This results in a phosphorus implant requirement of ~1keV. Depletion in the poly Si gate requires a few keV implant energy for poly doping for both NMOS and PMOS. In order to maintain proper gate operation, gate doping requires around E15 doses. This places a large amount of implanted phosphorus at or near the surface of the wafer.In this paper, a phenomenon is described where the magnitude of surface particles arising from phosphorus implants is a function of the reaction between implanted phosphorus and ambient atmosphere. Using SEM/EDX, spatial and morphological descriptors of the defect types arising from these reactions have been classified. The implications of these results will be discussed from both a process perspective, in terms of accumulated dose and implant energy, and a time-based effect whereby defects grow over time both in number and size. Mitigation paths for particle metrology are proposed, and guidelines for Fab operators in terms of material storage and particle monitoring protocols described, in particular the criticality of time to measurement and maximum implanted dose.
机译:先进存储设备从平面结构到3D结构的演变已导致半导体设备制造商在交付可同时满足其客户的生产率,可靠性和工艺要求的产品方面面临前所未有的挑战。在离子注入领域,这些挑战受到以下因素的驱使:(i)硬掩模的普及和PR剥离工艺的取消,以及(ii)从在掺杂剂应用中使用注入到材料改性的过渡。这些已导致植入步骤可容许的粒度和数量密度的大幅降低。这些问题已被证明具有挑战性的领域之一是接触工程。低能磷注入用于提高多晶硅触点的接触电阻率。这对于DRAM操作中存储节点电容器的读/写时间至关重要。随着器件的进一步缩小,外围晶体管中的多晶硅栅的厚度将低至几百埃。这导致〜1keV的磷注入要求。多晶硅栅极的耗尽需要几keV的注入能量才能对NMOS和PMOS进行多晶硅掺杂。为了维持适当的栅极操作,栅极掺杂需要大约E15剂量。这将大量的磷注入到晶片的表面或附近。在本文中,描述了一种现象,其中磷注入产生的表面颗粒的大小是磷注入与周围大气之间反应的函数。使用SEM / EDX,已归因于这些反应的缺陷类型的空间和形态描述符已被分类。这些结果的含义将从过程角度(从累积剂量和植入能量的角度)以及基于时间的效应(缺陷和缺陷随数量和尺寸随时间增长)的角度进行讨论。提出了用于颗粒计量的缓解途径,并针对材料存储和颗粒监测协议,特别是测量时间和最大植入剂量的关键性,针对Fab操作员的指南进行了描述。

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