首页>
外国专利>
Use of Poly Resistor Implant to Dope Poly Gates
Use of Poly Resistor Implant to Dope Poly Gates
展开▼
机译:使用多晶硅电阻注入掺杂多晶硅浇口
展开▼
页面导航
摘要
著录项
相似文献
摘要
A process of fabricating an IC is disclosed in which a polysilicon resistor and a gate region of an MOS transistor are implanted concurrently. The concurrent implantation may be used to reduce steps in the fabrication sequence of the IC. The concurrent implantation may also be used to provide another species of transistor in the IC with enhanced performance. Narrow PMOS transistor gates may be implanted concurrently with p-type polysilicon resistors to increase on-state drive current. PMOS transistor gates over thick gate dielectrics may be implanted concurrently with p-type polysilicon resistors to reduce gate depletion. NMOS transistor gates may be implanted concurrently with n-type polysilicon resistors to reduce gate depletion, and may be implanted concurrently with p-type polysilicon resistors to provide high threshold NMOS transistors in the IC.
展开▼