An aging-aware model for the leakage power of nanoscaled digital integrated circuits in IoT era

摘要

Complementary metal oxide semiconductor (CMOS) transistors are considered as dominant technology in semiconductor industry. However, downscaling these transistors, despite of many achievements, has resulted in the rise of reliability issues. Environmental parameters namely temperature and power supply as well as circuit parameters such as duty cycle and frequency also time effect can lead to variations in some circuit characteristics. The large dependency of leakage power to the variations of parameters increases the importance of modeling. This paper is intended to introduce a new aging-aware model in order to calculate the leakage power consumption. Firstly, the leakage power as a function of these parameters, making use of the proposed model, is calculated for standard cells. Next, the power consumption of the same standard cells are measured by HSPICE. Next, we apply this model which is additive to calculate the leakage power of ISCAS85 and ISCAS89 benchmark circuits for 32nm and 22nm CMOS technology. Finally, the accuracy of this model is evaluated by comparing the calculated results from the additive model and HSPICE full-chip simulation results. We demonstrate that our simple yet accurate and additive model results in the maximum 4.74% mean percentage error.