Ultra shallow junctions <500 A with steep profiles <8nmldecade are required for device technologies ≤0.13 μm as outlined by the recent ITRS Roadmap. For a p{sup}+/n junction such profiles can be obtained using sub-keV B ion implantation since both the projected range and ore importantly the transient enhanced diffusion are significantly reduced at lower energies. State-of-the-art high current implanters utilize deceleration mode typically for sub 1 keV implantation in order to increase beam current and production wafer throughput. Such mode contains a very low level of energy contamination. This level is measured for sub keV B implants in the Quantum Leap and factors affecting the level of contamination are studied. Spike and soak annealing reduces the effect of the energy contamination on junction file and depth. The effect of energy contamination on device performance such as L{sub}(eff), V{sub}T and I{sub}(DAST) is simulated g ISE TCAD.
展开▼
