Electronic packages with fine pitch copper pillar bump interconnect and thin coreless substrate has become a satisfying solution for advanced integrated circuit (IC) to achieve miniaturization and high performance. However, non-wetting and poor interconnection issues of small and fine pitch copper pillar bumps due to large warpage of thin coreless substrate are the most common failure phenomenon during flip chip reflow process. In this work, the warpage of thin two layer coreless substrate during flip chip reflow process is comprehensively studied by using Shadow Moiré technique. A few design options are proposed and analyzed by DOE methodology, including prepreg stack-up design, metal trace design, designs with different metal layer thickness and solder mask thickness. These design options are then studied to understand their effectiveness for warpage improvement, and to figure out the optimized designs for minimum substrate warpage. From the results, it is found that the prepreg stack-up design is not effective for warpage reduction, but a significant option for improving warpage consistency at different location through the whole substrate strip during reflow process, choosing proper lamination process is helpful and important. Increasing metal layer thickness is an effective way for warpage improvement. Thick metal layer is not only beneficial for warpage reduction but also shows more consistency of warpage at different location through the whole substrate strip. It is also found that the thinner solder mask is an effective way for warpage reduction and warpage consistency improvement. Metal trace design is not effective for substrate warpage improvement. Final optimized design is obtained to improve substrate warpage, and to eliminate non-wetting and poor interconnection issues. The assembly yield of flip chip process can be substantially improved from 85.7% in preliminary design to 99.7% after optimization.
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