integrated circuit reliability; moulding; tape automated bonding; wafer level packaging; μbump; 3D IC packages; 3D package reliability; 3D stacks; HTS; IC assembly materials; Jedec standard reliability tests; MSL; Moore law; NUF; PCT; TCT-B; TSV processing; WLUF; bump pitches; capillary underfills; daisy chain; electrical tests; jetting parameters; low CTE epoxy mold compound materials; mass reflow chip attach process; no flow underfills; package robustness; processing complexities; reliability readouts; selection process; staging conditions; storage conditions; terms delamination; test vehicle; thermocompression bonding; thickness variations; underfill material; wafer level underfill; warpage behavior; Compounds; Lamination; Materials; Semiconductor device reliability; Stacking; Three-dimensional displays;
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