Analysis of the Output Conductance Degradation With the Substrate Bias in SOI UTB and UTBB Transistors

摘要

The goal of this work is to present the behavior of the output conductance in Ultra-Thin Body (UTB) and Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with the application of a selected set of back gate biases (VSUB) through AC simulations, in devices with and without considering the effect of the ground plane. It has been shown that the output conductance degradation due to self-heating and substrate effects increases as the substrate bias is reduced. The output conductance degradation by self-heating presents a reduction of about 52% and by substrate effects of 57% by simply increasing the back bias from -2V up to 2 V.