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Dynamic Substrate Bias for PMOS Transistors to Alleviate NBTI Degradation

机译:PMOS晶体管的动态衬底偏置可减轻NBTI退化

摘要

This invention discloses a system and method for suppressing negative bias temperature instability in PMOS transistors, the system comprises a PMOS transistor having a source connected to a power supply, and a voltage control circuitry configured to output a first and a second voltage level, the first and second voltage levels being different from each other, the first voltage level is lower than the power supply voltage, the second voltage level is equal to or higher than the power supply voltage, wherein when the PMOS transistor is turned on, the first voltage level is applied to a substrate of the PMOS transistor, and when the PMOS transistor is turned off, the second voltage level is applied to the substrate of the PMOS transistor.
机译:本发明公开了一种用于抑制PMOS晶体管中的负偏置温度不稳定性的系统和方法,该系统包括:PMOS晶体管,其源极连接到电源;以及电压控制电路,其被配置为输出第一和第二电压电平,第一第二电压电平互不相同,第一电压电平低于电源电压,第二电压电平等于或高于电源电压,其中,当PMOS晶体管导通时,第一电压电平施加到PMOS晶体管的衬底,并且当PMOS晶体管截止时,第二电压电平被施加到PMOS晶体管的衬底。

著录项

  • 公开/公告号US2010102872A1

    专利类型

  • 公开/公告日2010-04-29

    原文格式PDF

  • 申请/专利权人 WEI-HAO WU;ANTHONY OATES;

    申请/专利号US20080260982

  • 发明设计人 WEI-HAO WU;ANTHONY OATES;

    申请日2008-10-29

  • 分类号G11C5/14;G05F3/02;

  • 国家 US

  • 入库时间 2022-08-21 18:54:32

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