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Device Performance Evaluation of PMOS Devices Fabricated by B2H6PIII/PLAD Process on Poly-Si Gate Doping

机译:B 2 H 6 PIII / PIII / PIII / PIII / PIII / PIII / PIII / PIII / PIII / PLAD过程的PMOS器件的装置性能评估

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It has been shown that the PIII/PLAD poly-Si gate doping process offers unique advantages over conventional beam line systems, including system simplification, lower cost, higher throughput, and device performance equivalence or improvement. PMOS devices fabricated by a B2H6/H2PIII/PLAD process on P+poly-gate doping are intensively evaluated in this paper. In addition to higher throughput, PMOS devices fabricated by a PLAD process showed an equivalent electrical performance to those fabricated by conventional beam line ion implantation, including similar poly-Si gate resistance and depletion, threshold and sub-threshold characteristics, drive current, and gate-oxide integrity.
机译:已经表明,PIII / PLAD Poly-Si栅极掺杂工艺提供了与传统光束线系统相比的独特优势,包括系统简化,降低成本,更高的吞吐量以及设备性能等效或改进。 P + Poly-Gate上的B 2 H 6 / H 2 PIII / PLAD工艺制造的PMOS器件本文集中评估了掺杂。除了较高的产量之外,由Plad工艺制造的PMOS器件向由常规光束线离子植入制造的那些而言,包括相似的多Si栅极电阻和耗尽,阈值和子阈值特性,驱动电流和栅极 - 氧化物完整性。

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