It has been shown that the PIII/PLAD poly-Si gate doping process offers unique advantages over conventional beam line systems, including system simplification, lower cost, higher throughput, and device performance equivalence or improvement. PMOS devices fabricated by a B2H6/H2PIII/PLAD process on P+poly-gate doping are intensively evaluated in this paper. In addition to higher throughput, PMOS devices fabricated by a PLAD process showed an equivalent electrical performance to those fabricated by conventional beam line ion implantation, including similar poly-Si gate resistance and depletion, threshold and sub-threshold characteristics, drive current, and gate-oxide integrity.
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机译：已经显示出，PIII / PLAD多晶硅栅极掺杂工艺比常规束线系统具有独特的优势，包括系统简化，成本更低，产量更高以及器件性能相当或得到改善。通过P + 多晶硅栅上的B 2 H 6 / H 2 PIII / PLAD工艺制造的PMOS器件本文对掺杂进行了深入评估。除了更高的产量外，通过PLAD工艺制造的PMOS器件还具有与常规束线离子注入制造的器件相同的电性能，包括相似的多晶硅栅极电阻和耗尽，阈值和亚阈值特性，驱动电流和栅极-氧化物完整性。
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