Through-Silicon-Via (TSV) for silicon package: 'via-bridge' approach

摘要

We present in this paper an alternative Through-Silicon-Via approach that can meet the new requirements of Sipackage. In this wafer level packaging scheme, a thick silicon interposer (200 to 300μm) is directly reported ona PCB. In 200mm Si wafers, we made a two steps TSV composed of two vias: a top via and a bottom via. The topvia is etched with DRIE (diameter 60μm, depth 180 μm, Aspect Ratio = AR>3), and insulated with hightemperature dielectric. After dry film lithography, the TSV is partially plated with Cu limiting the process costs(short plating time, no CMP) and the stress inside the TSV. After temporary carrier bonding, the wafer isbackgrinded so that 15μm remains below the bottom of the main TSV. Backside lithography and DRIE processcreate the bottom via (four different diameters: 10-20-30 and 40μm) to contact main TSV. A final backside Cuplating of the opening completed the process. This via bridges the gap between via-last (AR<2) and via-middle(AR>7) and combines high temperature process from via-middle and low-cost processing from via-last. Themechanical simulations show that this "TSV bridge" has reduced residual stresses inside the TSV. Our electricalmeasurements exhibit an average single TSV resistance below 10mOhms with excellent yield (～95% on Kelvinand 82 TSV chains), and low contact resistances (4.7×10~(-9) Ω.cm~2) extrapolated on 4 different contact diameters.This 200μm deep TSV seems therefore very promising for low-cost thick interposer applications.