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Embedded package wafer bow elimination techniques

机译:嵌入式封装晶圆弯曲消除技术

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We outline several approaches to allow individual die to be encapsulated within a silicon substrate, which we define as a cavity wafer, without causing wafer bow. This technique forms the basis for a novel integrated ultra high density (i-UHD) wafer-level packaging platform. The iUHD process begins with a standard Si wafer that is patterned and dry etched to form cavities that accept buried components. After etching, the wafer is blanket metalized. Individual commercial off-the-shelf (COTS) die are placed onto an adhesive film and precision transferred to the substrate wafer. Low coefficient of thermal expansion (CTE) encapsulant is injected into the cavity surrounding the die. Finally, the adhesive film is removed to reveal a planar surface on the reconstructed core wafer. Multilayer interconnect is fabricated on both sides of the core using standard wafer fabrication techniques. A challenge to this approach has been that curing and shrinkage of the encapsulant, as well as its CTE mismatch with silicon, creates wafer bow. In this paper we present a technique that eliminates bow by mirroring the die-side wafer cavities about the neutral bending axis.
机译:我们概述了几种方法,可以将单个管芯封装在硅基板内,我们将其定义为空腔晶圆,而不会引起晶圆弯曲。该技术构成了新型集成超高密度(i-UHD)晶圆级封装平台的基础。 iUHD工艺始于对标准的Si晶片进行图案化和干法蚀刻,以形成可容纳掩埋元件的空腔。蚀刻之后,将晶片毯覆金属化。将各个商用现货(COTS)裸片放置在粘合膜上,并将其精确转移到基板晶圆上。将低热膨胀系数(CTE)密封剂注入到芯片周围的空腔中。最后,去除粘合剂膜以在重建的核心晶片上露出平坦的表面。使用标准晶圆制造技术,可以在内核的两侧制造多层互连。这种方法的挑战在于,密封剂的固化和收缩以及CTE与硅的不匹配会造成晶圆弯曲。在本文中,我们提出了一种通过绕中性弯曲轴镜像晶片侧晶片腔来消除弯曲的技术。

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