Decimal Floating Point Adder using Concatenated Reduced Delay BCD Adders

摘要

Man has always preferred decimal arithmetic as the base for his calculations. His ten fingers always made it easy to use decimal arithmetic. But, most of the modern day digital systems use binary as the base for operations. In real world systems, to enable accessibility by humans, software processing of decimal numbers is thus necessary. This causes an additional delay in the operation. The conversion from decimal to binary can reduce the accuracy too. If this decimal processing unit can be implemented in hardware, we can, thereby save a considerable amount of time. Addition is the most basic of operations. Whether the operation the system performing is multiplication, division or subtraction, the basic module in the system is an adder.