Adder circuit for serial addition of BCD 8421-coded decimal numbers

摘要

The serial adder circuit according to the subject of the invention has two dual full adders (1 and 2), of which the dual full adder (2) is intended for a possible correction addition of the number 6 (LHHL). The addition takes place in eight shift register cycles, of which the fifth cycle overlaps in time with the next first cycle, and the eighth cycle overlaps in time with the next fourth cycle. Thus, for each addition, four starting shift register cycles are required. After four cycles, the intermediate result number is stored in the shift register (6). If the intermediate result number is greater than the number 9 (HLLH), the number 6 (LHHL) is added in the sixth and seventh cycles. In these two cycles, there is high potential at input G. IMAGE