This paper describes a scalable and robust differential rail-to-rail delay cell. The delay cell is fabricated in a 3.3 V 0.35 urn CMOS process. The delay cell shows a wide-range operation and low power supply sensitivity. The delay range is 0.31 ps to 21.8 ns. For 0.5 ns delay, when the clock period is 500 MHz, the power supply sensitivity is 0.033 ps/mV. The delay cell is used in a DLL for clock generation of a four times interleaved 2 Gb/s decision feedback equalizer.
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