APPARATUS FOR A MONOTONIC DELAY LINE, METHOD FOR FAST LOCKING OF A DIGITAL DLL WITH CLOCK STOP/START TOLERANCE, APPARATUS AND METHOD FOR ROBUST CLOCK EDGE PLACEMENT, AND APPARATUS AND METHOD FOR CLOCK OFFSET TUNING

摘要

Described is an apparatus comprising: a delay line including at least four delay stages coupled together in a series; a first multiplexer having a first input coupled to an output of a first delay stage of the at least four delay stages, and a second input coupled to an output of a third delay stage of the at least four delay stages; a second multiplexer having a first input coupled to an output of a second delay stage of the at least four delay stages, and a second input coupled to an output of a fourth delay stage of the at least four delay stages; and a phase interpolator coupled to outputs of the first and second multiplexers, the phase interpolator having an output.