APPARATUS FOR A MONOTONIC DELAY LINE, METHOD FOR FAST LOCKING OF A DIGITAL DLL WITH CLOCK STOP/START TOLERANCE, APPARATUS AND METHOD FOR ROBUST CLOCK EDGE PLACEMENT, AND APPARATUS AND METHOD FOR CLOCK OFFSET TUNING

摘要

A delay line has at least four delay stages coupled together in a series, two multiplexers, and a phase interpolator. The first multiplexer has a first input coupled to an output of the first delay stage, and a second input coupled to an output of the third delay stage. Similarly, the second multiplexer has a first input coupled to an output of the second delay stage, and a second input coupled to an output of the fourth delay stage. The phase interpolator is coupled to outputs of the first and second multiplexers, and has an output.