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Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning
Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning
Described is an apparatus comprising: a delay line including at least four delay stages coupled together in a series; a first multiplexer having a first input coupled to an output of a first delay stage of the at least four delay stages, and a second input coupled to an output of a third delay stage of the at least four delay stages; a second multiplexer having a first input coupled to an output of a second delay stage of the at least four delay stages, and a second input coupled to an output of a fourth delay stage of the at least four delay stages; and a phase interpolator coupled to outputs of the first and second multiplexers, the phase interpolator having an output.
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