A Noise and Mismatches of Delay Cells and Their Effects on DLLs

摘要

Jitter is one of the most important parameters in design of delay locked loop (DLL) based frequency synthesizer. In this paper noise and mismatches of conventional delay cells which are mainly used in the DLLs architecture are introduced completely. First, time domain equations related to noise and mismatches of conventional delay cells are reported. Then, these equations are used to calculate jitter of DLL due to mismatch and noise of delay cells. At last closed form equations are obtained which can be used in the designing of low jitter DLLs. To validate these equations, a conventional DLL is designed in TSMC 0.18um CMOS Technology.