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Robust Underfill Selection Methodology for Flip Chip

机译:倒装芯片的可靠底部填充选择方法

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摘要

Underfill is one of the crucial materials in flip chip (FC) packages. The role of underfill is not only to protect the solder bumps but to minimize package warpage, and to protect the fragile low k dielectric at end of line (EOL), moisture resistance test (MRT), and temperature cycle B (TCB) conditions. As packages move towards green products, the complexity of selecting a good underfill increases. The interaction of high Pb or eutectic solder with the underfill is different than that of Pb free solder. Moreover Pb free solder behavior for FC bumps is just being explored in the literature. Besides Pb free solder, other parameters like die passivation, bump height and pitch, under bump metallurgy (UBM) metallization, and package substrate are also extremely important for underfill selection. As the design of the package continues to change smaller package, tighter bump pitch and thinner core and build up (BU) layers, all of these parameters are directly related to package reliability. Sometimes an underfill good for a smaller die, body size, taller bump height, and pitch doesn't necessarily mean it will be appropriate for a bigger die with larger body, and tighter bumps. So there are lots of variables in the package that directly affect the reliability. A good underfill should have very good adhesion between underfill and die passivation at room temperature, and moderate adhesion at underfill Tg. Adhesion properties are solely depend on chemistry of the underfill. Therefore to determine a good underfill for a bigger die and body size, we need to have a sequential selection methodology. In this paper a sequential selection methodology is used to eliminate the unsuccessful underfill candidates and select the best one which comfortably satisfies the requirements for all different solder alloys, and a wider range of package geometries. Important selection criteria including underfill workability issues and modeling data are also discussed.
机译:底部填充是倒装芯片(FC)封装中的关键材料之一。底部填充的作用不仅在于保护焊料凸点,而且还最大程度地减少了封装翘曲,并保护了线路末端(EOL),耐湿性测试(MRT)和温度循环B(TCB)条件下的易碎低k电介质。随着包装朝着绿色产品的方向发展,选择优质底部填充材料的复杂性会增加。高铅或共晶焊料与底部填充剂的相互作用与无铅焊料的相互作用不同。而且,FC凸块的无铅焊料行为只是在文献中进行了探讨。除无铅焊料外,其他参数(如芯片钝化,凸点高度和间距,凸点冶金(UBM)下的金属化以及封装衬底)对于底部填充的选择也非常重要。随着封装设计的不断变化,更小的封装,更紧密的凸点间距和更薄的内核和堆积(BU)层,所有这些参数都直接与封装的可靠性相关。有时候,底部填充对较小的模具,主体尺寸,较高的凸块高度和间距而言是有益的,但不一定意味着它适用于较大的模具和较大的凸块以及较紧的凸块。因此,程序包中有许多直接影响可靠性的变量。良好的底部填充胶在室温下应在底部填充胶与芯片钝化之间具有非常好的粘合性,而在底部填充胶的Tg上具有适度的粘合性。粘合性能仅取决于底部填充胶的化学性质。因此,为了确定更大的模具和主体尺寸的良好底部填充,我们需要有一种顺序选择方法。在本文中,采用顺序选择方法来消除不成功的底部填充候选物,并选择能够舒适地满足所有不同焊料合金的要求以及更广泛的封装几何形状的最佳填充方法。还讨论了重要的选择标准,包括底部填充可加工性问题和建模数据。

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