Drain leakage fluctuation reduction in the recessed channel array transistor DRAM with the elevated source-drain

摘要

Gate induced drain leakage (GFDL) characteristics were investigated with the recessed channel array transistor (RCAT) for DRAM, using the elevated source drain (ESD). The lower doping concentration of a source-drain region in the ESD structure reduces the electric field, which reduces drain leakage current and also the fluctuation of leakage current These reductions can enhance the data retention time of DRAM. The reduced electric field also improves hot carrier immunity of the cell transistor as well.