机译:具有三端栅极控制二极管的低于50 nm凹沟道型DRAM单元晶体管的漏电流机制
Process Development Team, Semiconductor R&D Center, Samsung Electronics Company, Ltd., Hwasung-city, Kyunggi-do 445-701, Republic of Korea,Department of Electrical Engineering, Korea University, Anam-dong, Seongbuk-gu, Seoul 136-701, Republic of Korea;
Process Development Team, Semiconductor R&D Center, Samsung Electronics Company, Ltd., Hwasung-city, Kyunggi-do 445-701, Republic of Korea;
Process Development Team, Semiconductor R&D Center, Samsung Electronics Company, Ltd., Hwasung-city, Kyunggi-do 445-701, Republic of Korea;
DRAM Characteristic Research Team, Semiconductor R&D Center, Samsung Electronics Company, Ltd., Hwasung-city, Kyunggi-do 445-701, Republic of Korea;
Process Development Team, Semiconductor R&D Center, Samsung Electronics Company, Ltd., Hwasung-city, Kyunggi-do 445-701, Republic of Korea;
Process Development Team, Semiconductor R&D Center, Samsung Electronics Company, Ltd., Hwasung-city, Kyunggi-do 445-701, Republic of Korea;
Process Development Team, Semiconductor R&D Center, Samsung Electronics Company, Ltd., Hwasung-city, Kyunggi-do 445-701, Republic of Korea;
DRAM Characteristic Research Team, Semiconductor R&D Center, Samsung Electronics Company, Ltd., Hwasung-city, Kyunggi-do 445-701, Republic of Korea;
Process Development Team, Semiconductor R&D Center, Samsung Electronics Company, Ltd., Hwasung-city, Kyunggi-do 445-701, Republic of Korea;
Department of Electrical Engineering, Korea University, Anam-dong, Seongbuk-gu, Seoul 136-701, Republic of Korea;
gate-controlled diode; leakage current; cell transistor; rcat; mosfet;
机译:50纳米以下的隐通道型DRAM单元晶体管中的界面陷阱的空间分布
机译:低于50 nm DRAM单元晶体管的具有不重叠的源极/漏极至栅极的局部隔离沟道FinFET的特性
机译:低于50 nm DRAM单元晶体管的具有不重叠的源极/漏极至栅极的局部隔离沟道FinFET的特性
机译:一种新的低漏电流VPT(垂直柱晶体管)集成为4F {SUP} 2 DRAM单元阵列,具有SUB 40 NM技术
机译:独立双栅极SOI MOSFET晶体管泄漏电流的仿真分析。
机译:高性能和低功耗单片三维3μm以下50微米多晶硅薄膜晶体管(TFT)电路
机译:用于亚50nm DRam单元晶体管的局部分离通道结构的体FinFET的设计考虑