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Flip chip attach with thermoplastic electrically conductive adhesive

机译:倒装芯片附有热塑性导电胶

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A set of processes has been developed and demonstrated to interconnect flip chips with an electrically conductive adhesive material to laminates. Paste deposition uses a photolithography process to define room temperature stable thermoplastic conductive adhesive bumps that are 0.2 mm in diameter and 0.1 mm high. Photobumping is done at wafer level, and dicing yields chips that are ready for attachment to a carrier. Chip bonding process development defined a process window and identified an optimal process point. Repeatable tensile bond strengths between 10 and 14 MPa can be achieved. Fracture mode typically occurs near an interface but in the joint material. Bonding temperature, pressure, and pressure on cool-down (to 120/spl deg/C) were identified as key process variables. The optimum bonding process point is applying one MPa to the chip, while heating to 235/spl deg/C. Pressure is maintained for 30 seconds at temperature and until cooled to 70/spl deg/C. These optimum bond parameters resulted in bond lines of 0.05/spl plusmn/0.005 mm. The harshest stress test is deep thermal cycling for both blanket and stitched chip designs. The interconnect performance on the blanket chip is comparable to soldered flip chip on laminate. The interconnect performance on the stitch chip is less robust. It is believed that reaction between the photobumping stripper and the polyimide passivation results in a weak interface between the adhesive bump and card metallurgy. Results from stress testing demonstrate the design feasibility of electrically conductive adhesive interconnects for flip chip attach to laminates.
机译:已经开发并证明了一组工艺,该工艺将具有导电粘合剂材料的倒装芯片互连到层压板。糊剂沉积使用光刻工艺来定义直径为0.2毫米,高度为0.1毫米的室温稳定的热塑性导电胶块。光电凸块在晶圆级完成,切块会产生准备好附着在载体上的芯片。芯片键合工艺开发定义了工艺窗口并确定了最佳工艺点。可以实现10到14 MPa之间的可重复拉伸强度。断裂模式通常发生在界面附近但在接头材料中。键合温度,压力和冷却压力(至120 / spl deg / C)被确定为关键工艺变量。最佳的粘合工艺点是对芯片施加1 MPa的压力,同时加热到235 / spl deg / C。将压力在该温度下保持30秒,直到冷却至70 / spl deg / C。这些最佳的粘合参数导致粘合线为0.05 / spl plusmn / 0.005 mm。最严酷的压力测试是对毯式和缝合式芯片设计进行深层热循环。覆盖芯片上的互连性能可与层压板上的焊接倒装芯片相媲美。针脚芯片上的互连性能较差。可以认为,光起泡剥离剂和聚酰亚胺钝化之间的反应导致粘合剂凸块和卡片冶金之间的界面较弱。应力测试的结果证明了用于倒装芯片连接到层压板的导电胶互连件的设计可行性。

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