Process and device simulation in designing thin film CMOS/SOI technology

摘要

The authors report on process modeling used FEDSS (Finite Element Diffusion Simulation System) together with device modeling using FIELDAY (FInite ELement Device AnalYsis) to analyze fully depleted thin film SOI (silicon-on-insulator) processes/devices. The FEDSS output after simulating drain implantation is presented, showing drain profile and polysilicon side wall oxides. Channel doping for both p- and n-type devices was p-type, and FEDSS modeling from process parameters found the device channel doping to be 8*10/sup 15//cm/sup 3/, tailing off in the 100 AA gate surface 6*10/sup 15//cm/sup 3/ due to boron depletion. Measured results for the n-channel device were compared with the FIELDAY simulations. The difference between calculation and measurements increases for higher gate voltages. After the DC terminal characteristics were reconciled, the breakdown characteristics of the models were investigated.