BALL STACK PACKAGING FOR HIGH PERFORMANCE MEMORY

摘要

The new generations of dynamic random access memoryrn(DRAM) and synchronous dynamic random access memoryrn(SDRAM) technologies are contributing significantlyrntoward increased system performance. Improvement inrnprocessing speed, however, can be hampered by inefficiencyrnin both package performance and module-level interconnect.rnFurthermore, these high performance memory die have beenrndesigned with center bond pads rather than the peripheralrnbond format more common in earlier applications. Thernchange in die layout, although challenging for traditionalrnlead-frame package technology, has proved ideal for arrayrnpackaging.rnThe array format package with the die facing downrnfurnishes a much shorter circuit path than lead-framernpackaged die, minimizing the signal path between die andrnthe printed circuit board (PCB) structure. For this reason,rnthe developers of Rambus DRAM (RDRAM) and dual datarnrate (DDR) DRAM have found that array type packagesrnenable optimized memory performance. To enable higherrndensity memory, Tessera has developed a package stackingrnprocess the company has defined the “μZ? Ball-Stack”rnpackage. The package technology is targeted for a variety ofrnmemory as well as multiple-function applications, however,rnto be widely adopted the ball-stack methodology must bernsubjected to extensive qualification and reliability testing.