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Effect of Drain Top Metal Overlap on the Current in Bottom-gate Thin Film Transistors

机译:漏极顶部金属重叠对底栅薄膜晶体管电流的影响

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In this paper we analyze the effect of the top metal overlap associated to the drain contact, that can be present in thin film transistors (TFTs) with bottom-gate staggered configuration. It is shown that the effect of the top metal contact at the drain, overlapping the passivation or etch stopper layer (ESL), increases the drain current. Results from numerical simulations show that this top metal overlap acts as a second gate to the device, partially located near the drain contact. The overall effect on the device current will depend on the semiconductor doping, as well as on the thickness and dielectric constants of the gate dielectric and passivation/ESL layers. The effect is more significant as the channel length of the devices is reduced.
机译:在本文中,我们分析了与漏极接触相关的顶部金属重叠的影响,这种影响可能出现在具有底部栅极交错配置的薄膜晶体管(TFT)中。结果表明,与钝化层或蚀刻停止层(ESL)重叠的漏极上的顶部金属接触的影响会增加漏极电流。数值模拟的结果表明,这种顶部金属重叠部分是器件的第二个栅极,部分位于漏极触点附近。对器件电流的总体影响将取决于半导体掺杂,以及栅极电介质和钝化/ ESL层的厚度和介电常数。随着设备通道长度的减小,效果会更加显着。

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