the Department of Electrical Engineering Section of Solid State Electronics CINVESTAV-IPN Av. IPN. No. 2508 Mexico City CP 07360;
Consiglio Nazionale delle Ricerche (CNR) Instituto per la Microelettronica e Microsistemi (IMM) Area della Ricerca Roma 2 Via del Fosso del Cavaliere 100 00133 Roma;
Metals; Logic gates; Thin film transistors; Passivation; Current density; Dielectrics;
机译:底部栅极非晶IGZO薄膜晶体管低漏极电流范围内的低频噪声起因
机译:具有固有蚀刻停止和退火引起的源极和漏极区域的底栅铟镓锌氧化物薄膜晶体管
机译:通过施加偏压力减小通过盖层多晶硅薄膜晶体管的底栅N沟道金属诱导的结晶中的漏电流
机译:漏极顶部金属重叠对底栅薄膜晶体管电流的影响
机译:带有金属置换的源极和漏极的薄膜晶体管
机译:氧含量对底栅非晶InGaZnO薄膜晶体管电流应力诱导的不稳定性的影响
机译:以Cu / CuMg为源极/漏极金属的岛状非晶硅薄膜晶体管中肖特基漏电流的抑制