首页> 外文会议>International Symposium on Microelectronics; 20050925-29; Philadelphia,PA(US) >Wire Looping Optimization in Fine Pitch Dual Row In-line Pad Devices
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Wire Looping Optimization in Fine Pitch Dual Row In-line Pad Devices

机译:细间距双排直插式焊盘设备中的线环优化

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Fine pitch wire bond technology for IC devices continues to evolve. More challenging designs have been developed in order to provide opportunities for tighter pitch, smaller die size, more die per wafer, as well as provide more functionality to customers. The traditional in-line bond pad design would utilize smaller bond pads and smaller wire diameter and capillary, which creates a myriad of assembly processing and reliability difficulties. The industry is still very reluctant to embark on volume production at 35um pitch using 15um wire diameter. Staggered bond pad designs provide a tighter effective pitch while employing less aggressive assembly technology. However, this design layout tends to have large die corner keep-out, thus increasing die size. Dual row in-line bond pad layouts have now emerged, where two rows of bond pads are placed around the die perimeter, in line in both the X and Y directions. In a 47pm dual in-line pad layout (44um pad width and minimum 3um between pads), the effective pitch of 23.5um can be achieved with a 20um wire diameter. However, there are numerous challenges in wire bonding a dual row in-line bond pad design. These challenges include: the ability to create multiple wire tiers and special wire looping to ensure no wire shortage between the rows, clearance between the top of the encapsulation and the tallest loop, and long wire length to accommodate high I/O count. This paper will begin with a brief description of the 47um pad pitch dual in-line pad design. The paper then focuses on the assembly challenges associated with dual in-line design. Systematic experiments were conducted to evaluate the wire bonder's stability in forming different wire loop heights, kinks, and lengths consistently. Evaluations on die thickness on different package platforms were carried to define the die thickness necessary to allow sufficient clearance above the Silicon and the top of the encapsulation. Wire bond parameter optimization was critical to achieve both ball size reduction and bond strength stability. Wire loop height and scheme were optimized to minimize wire sweep during encapsulation. Package reliability testing was also performed. The 47um dual in-line design can indeed deliver a robust fine pitch solution without stretching assembly into ultra fine pitch production.
机译:用于IC器件的细间距引线键合技术正在不断发展。为了提供更紧密的间距,更小的管芯尺寸,每个晶圆更多的管芯以及为客户提供更多功能的机会,已经开发出更具挑战性的设计。传统的在线键合焊盘设计将利用较小的键合焊盘以及较小的导线直径和毛细管,这会产生大量的组装过程和可靠性难题。业界仍然非常不愿意以15um的线径以35um的间距开始批量生产。交错的键合焊盘设计提供了更紧密的有效间距,同时采用了较少侵蚀性的组装技术。然而,这种设计布局往往具有较大的裸片拐角保持空间,从而增加了裸片尺寸。现在已经出现了双行串联键合焊盘布局,其中两行键合焊盘在管芯周边沿X和Y方向并排放置。在47pm的双列直插式焊盘布局中(焊盘宽度为44um,焊盘之间的最小间距为3um),使用20um的线径可以实现23.5um的有效节距。然而,在引线键合双行串联键合焊盘设计中存在许多挑战。这些挑战包括:创建多个导线层的能力和特殊的导线环以确保各行之间没有导线短缺,封装顶部和最高回路之间的间隙以及较长的导线长度以容纳较高的I / O数量。本文将以47um焊盘间距双列直插式焊盘设计的简要说明开始。然后,本文重点讨论与双列直插式设计相关的组装挑战。进行了系统的实验,以评估引线键合机在始终如一地形成不同的导线环高度,扭结和长度方面的稳定性。进行了在不同封装平台上的管芯厚度评估,以定义必要的管芯厚度,以允许在硅和封装顶部上方留出足够的间隙。线键合参数优化对于实现减小焊球尺寸和键合强度稳定性至关重要。优化了线环的高度和方案,以最大程度减少封装过程中的线扫。还进行了包装可靠性测试。 47um双列直插式设计确实可以提供强大的细间距解决方案,而无需将组件扩展到超细间距生产中。

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