Channel Engineering of Buried-Channel 4H-SiC MOSFET Based on the Mobility Model of the Oxide/4H-SiC Interface

摘要

The channel mobility in the vicinity of the silicon carbide (SiC)/oxide interface is modeled from the measured mobility of a surface channel SiC MOSFET and a buried-channel MOSFET. With this channel mobility model, channel engineering of a buried-channel SiC MOSFET has been done. In an optimized structure, a p-type layer is stacked between oxide and buried channel in order to avoid the mobility degradation due to the interface. Device simulation shows a remarkable increase of drain current in a p-type layer-stacked buried-channel (PLBC) MOSFET.