Use of Paraplanar Constraint for Parallel Inspection of Wafer Bump Heights

摘要

The shrunk dimension of electronic devices leads to more stringent requirement on process control and quality assurance of their fabrication. For instance, direct die-to-die bonding requires placement of solder bumps not on PCB but on the wafer itself. Such wafer solder bumps, which are much miniaturized from the counterparts on PCB, still need to have their heights meet the specification, or else the electrical connection could be compromised, or the dies be crushed, or even the manufacturing equipments be damaged. Yet the tiny size and the texturelessness and mirror nature of the bumps pose great challenge to the 3D inspection process. This paper addresses how a large number of such wafer bumps could in parallel have their heights checked against the specification without the 3D metric information of individual bumps nor their average height be reconstructed explicitly. The system involves two pairs of illumination-plus-camera equipments, and the use of a 3×3 inspection quality matrix that is extracted from the image data. The system is further improved by exploiting the fact that the plane of the bump peaks and plane of the bump bottoms can well be regarded as parallel because the visual field of the inspected die in the image data is small. Experimental results are shown to illustrate the effectiveness of the inspection system.