Micro inspection for wafer bumping: Inspection requirements for wafer-level packaging processes

摘要

Driven by consumer demand for electronic products of both high performance and compact size, the number of integrated circuits (IC) being packaged in flip-chip or wafer-level schemes has increased dramatically in recent years. The demand for bumped wafers for flip chip in package (FCIP) and flip chip on board (FCOB) will increase at a compound annual growth rate of more than 35 percent through 2005, according to one report. As wafer bumping continues to grow, automated inspection and metrology in bumping and other wafer-level packaging (WLP) processes have become increasingly important. Because the design rules associated with bumping and WLP are considerably relaxed compared to those in front-end wafer processing, sub-micron inspection is not necessary. Defect detection and metrology measurements with sensitivity of one or more microns are generally sufficient. However, inspection for these applications does present a number of unique challenges.