Challenges of integration of porous low-k dielectrics and advanced barrier materials

摘要

The development of robust integration processes for low-dielectric-constant materials is critical in order to meet the International Technology Roadmap for Semiconductors (ITRS) timeline for next-generation materials. Organosilicate glass (OSG) materials with bulk dielectric constant between 2.7 and 3.0 are currently being ramped into production for the 90nm and 65nm semiconductor devices interconnect node. For 45 nm and beyond, the ITRS roadmap dictates use of an advanced dielectric material with a bulk dielectric constant below 2.5. The dielectric constant of OSG materials produced by plasma-enhanced chemical vapor deposition (PECVD) processes can be reduced to less than 2.0 through the introduction of nanometer-scale porosity. During integration of these porous materials, liquids can be absorbed into the pore network (e.g. during the polishing and cleaning process steps) resulting in an increase in the dielectric constant. The ease of removal of the penetrating species will be dependent on its polarity, wetting characteristics, molecular weight, and reactivity with the OSG network. High molecular weight species that easily wet the surface or reactive chemical species will be very difficult to remove by subsequent processing steps. The key to understanding the penetration of process chemicals into porous low-k dielectric materials is being able characterize the mass transport rate and accessible porosity of various compounds into the porous network.