A new 600V lateral PMOS device with a buried conduction layer

摘要

This paper reports a new 600V lateral PMOSFET with the lowest specific on-resistance ever reported. The novel device is fabricated in bulk silicon using high-energy implantation to form a buried P-type conduction layer within an Nwell. Experimental devices exhibit breakdown voltage of 660V and specific on-resistance of 60 ohm-mm², which is about 50% lower than the state-of-art based on T. Letavic et al. (2002). The device structure, simulations, fabrication process, and experimental results are presented.