Board Level Assembly and Rework Assessment of Thin Substrate Chip Scale Package (tsCSP), a Multi-Row Leadless Package

摘要

In recent years, Quad Flat No-lead (QFN) packages have gained rapid industry acceptance due to their compact size combined with superior electrical and thermal characteristics. Just as the industry becomes accustomed to the standard Leadframe-based QFN devices, the need for higher performance leadless packages are emerging. The Thin Substrate Chip Scale Package (tsCSP) is a leadless multi-row packaging solution that offers design flexibility and accommodates more I/Os than typical QFN devices. It also provides an isolated power/ground ring option for enhanced electrical characteristics. This paper will focus on the surface mount assembly aspect of this leadless package. It will provide guidelines for board level assembly and rework processes, based on extensive surface mount experiments. A 10 mm, 200 I/O, 0.5 mm pitch (both in X and Y direction), 3-row version of the tsCSP package was considered for this evaluation. X-ray inspection and cross-section results were analyzed to understand the influence of various design and process parameters on solder joint standoff height and voiding. Both aqueous and no-clean lead-free solder paste chemistries were evaluated. Challenges and concerns related to cleaning underneath these low profile parts will also be discussed.