A Hierarchical Method to Perform IR Drop and Electromigration Analysis for Faster Tape-out of Analog-on-Top Designs

摘要

The post-layout verification of large analog circuits requires a substantial amount of time. As feature sizes, such as wire width, continually decrease and performance requirements increase, the performance loss due to IR drop, and critical failures due to Electromigration (EM) are more likely to occur. These issues must be assessed during post-layout verification, so that faster verification methods are of great benefit. This paper presents a hierarchical analysis method to reduce post-layout verification time in consideration of IR drop and EM issues. The proposed method minimizes postl-ayout simulation time without an increase in error margins, so that pre-defined design constraints remain satisfied. The new method is applied to a large analog block. Results are discussed and layout guidelines and recommendations are presented to achieve high accuracy.