PURPOSE: A method for analyzing the IR Drop of ASIC(Application Specified IC) design is provided to prevent Floorplan step return by analyzing the IR drop at a time point completing Floorplan and Placement. CONSTITUTION: A power network is formed for analyzing a power grid(SP1). After detecting current and resistance of entire ASIC design by generating an equivalent current resistance model for each row, a power rail resistance model is generated by using the current and the resistance(SP2). A supply voltage applied by each instance is calculated(SP3). The voltage and the IR drop applied to a power port of each instance are calculated by using the calculated supply voltage(SP4).
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机译:目的:提供了一种用于分析ASIC(应用指定的IC)设计的IR Drop的方法,以通过在完成Floorplan and Placement的时间点分析IR drop来防止Floorplan步骤返回。构成:形成一个用于分析电网(SP1)的电网。在通过为每一行生成等效电流电阻模型来检测整个ASIC设计的电流和电阻之后,通过使用电流和电阻(SP2)生成电源轨电阻模型。计算每个实例施加的电源电压(SP3)。通过使用计算出的电源电压(SP4)来计算施加到每个实例电源端口的电压和IR降。
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