Statistical Simulation to Predict Variability of TANOS Program/Erase Characteristics for Non-Volatile Memory Applications

摘要

The impact of device-to-device statistical variation on Program/Erase (P/E) transients of planar TANOS devices is investigated using a multi-scale simulation approach. Atomic-level material and defect properties are first extracted from experimental results and then employed to study variability of the flat-band voltage shift. Erase characteristics are observed to be more affected by statistical variation. Interestingly, by adjusting temperature, gate voltage and/or blocking layer thickness, an optimized operating condition can be reached such that variability in 3D TANOS arrays is minimized.