60-nm Gate Length SOI CMOS Technology Optimized for 'System-on-a-SOI-Chip' Solution

摘要

In this paper, we describe 60-nm gate length SOI CMOS technology for "system-on-a-SOI-chip" solution. This concept features that: 1) high speed logic circuits are designed with PDSOI in order to enhance operation speed, 2) the remaining circuits which require stable body potential are designed with body-slightly-tied SOI (BSTSOI~(TM)), in which body potential is fixed with no area penalty. With newly developed self-aligned dual trench isolation (SDTI), both PDSOI and BSTSOI can be fabricated on the same die. We compare PDSOI and BSTSOI with bulk CMOS devices in terms of transistor characteristics and circuit performance including SRAM static noise margin as well as soft error immunity, In addition, we demonstrate stacked metal-insulator-metal (MIM) capacitor DRAM cell fabricated on BSTSOI.