Control of SEU in SOI SRAMs Through Carrier Lifetime Engineering

摘要

SOI technologies have long been used for SEU-hardened SRAMs and other radiation hard circuits. However, to maintain their advantages in the submicron regime, it is essential that the strength of the FBE and the implied parasitic bipolar transistor (BJT) should be minimized. In this work, this is best achieved by reducing the gain p of the parasitic BJT without degrading the SRAM performance, by controlling the carrier lifetime of the SOI film. Two sets of devices (Ⅰ and Ⅱ) were fabricated on 0.35 μm PD SOI technology where Device Ⅱ underwent a lifetime killing-processing step to control SEU vulnerability. These devices were experimentally characterized and simulated, and the results verified the benefits of lifetime killing.